This invention relates to integrated circuits, in particular to integrated circuits that are designed using logic cells selected from a cell library.
Within an integrated circuit, complicated circuitry is generally fashioned by interconnecting pre-designed cells that perform simple functions such as logic gates, latches, flip-flops, etc.; or more complex functions such as counters, registers, etc. Each cell must be connected to power and ground, commonly referred to as Vdd and Vss, in order to function.
In order to provide Vdd and Vss throughout the integrated circuit, a power grid is defined which is fashioned from the various levels of conductive interconnects. Since the power grid is defined prior to laying out the integrated circuit, there are often conflicts in placing the various cells that form the integrated circuit which results in a sub-optimum circuit layout.
An object of the present invention is to provide a dynamic power grid construction methodology that allows optimum placement of the various cells that form an integrated circuit.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
In general, and in a form of the present invention a method for designing an integrated circuit which contains a number of high power logic cells, a number of low power logic cells and several interconnect layers is provided. A power grid is defined which has a first set of buses on a first of the interconnect layers and a second set of buses on a second of the interconnect layers. Both sets of buses are oriented horizontally and positioned approximately coincidentally. A layout of the integrated circuit is created by placing low power logic cells and high power logic cells in a horizontal row in such a manner that a position along the row of each low power logic cell and each high power logic cell is not constrained by a pre-positioned power tap within the power grid. Each low power logic cell is connected to a power bus in the first set of buses and each high power logic cell is connected to a power bus in the second set of buses.
In another form of the present invention, a third set of buses is placed on a third of the interconnect layers and oriented in a vertical manner. The third interconnect layer is place on top of the first two interconnect layers and a set of interconnects are formed between the third set of buses and the second set of buses. If there is a conflict between a logic cell and one of these interconnects, the interconnect is deleted.
In another form of the present invention, a fourth and fifth interconnect layer are used for routing signal interconnections between the logic cells. The fourth and fifth interconnect layers are placed between the first and second interconnect layers.
In another form of the present invention, a low power grid is defined which is sufficiently robust to supply power for the set of low power logic cells. A layout of the integrated circuit is created in which all of the logic cells are connected to the low power grid. The integrated circuit design is then simulated to determine dynamic power requirements of each logic cell. A power contour map is formed which represents the location of logic cells which have a high dynamic power requirement. A high power grid is defined which covers high power areas of the integrated circuit and the high power logic cells are connected to the high power grid.
Other embodiments of the present invention will be evident from the description and drawings.